This invention relates in general to radio frequency (RF) receivers and more particularly to control of receiver dynamic range.
With the increasing demand for multi-mode/multi-band wireless products, there is a need for cost effective architectures such as direct conversion radio frequency (RF) receivers. The use of a dynamic range on demand direct conversion architecture (this invention) provides a high performance receiver with long battery life, reduced parts count and shortened manufacturing time. In the past, many electronic devices using other architectures have had a reduced battery life, increased battery size and/or cost due to the required use of more complex battery chemistries. By way of example, the conventional direct conversion code division multiple-access (CDMA) receiver requires approximately twice as much current drain in the RF to analog-to-digital (A/D) line up which has a major impact on the receive mode current drain.
With regard to CDMA, increased competition in the wireless market has driven receiver topology designs to their most cost effective solutions. These new architectures typically make the system less complex and cross platform. This cost savings has resulted in the removal of passive selectivity such as surface acoustic wave (SAW) or crystal filters to reduce cost and a broadening of the analog-to-digital (A/D) converter specifications to meet the multi-MA (Multi Access) requirements. Active integrated circuits provide a cost effective method in which to implement these new architectures.
Currently there are no new methods in which to implement a passive highly selective or high quality factor (Q) filter onto an integrated circuit silicon based process. Thus, for a given integrated circuit process, the current drain will increase as any new receiver designs remove off chip passive selectivity. When large signals are present and no passive selectivity is used to protect the active circuitry, the active circuits will have to operate when weak and very strong signals exist simultaneously. With passive selectively, large alternate signals are attenuated before the active circuitry, thus reducing its strength at the active circuits. New cost effective architectures with integrated circuit solutions will thus have to handle a larger range of signals.
Prior art FIG. 1 shows an exiting receiver zero intermediate frequency (ZIF) architecture 100 for a CDMA handset. As is known in the art, the 3 dB low-pass bandwidth of the CDMA signal is approximately 620 KHz. Due to the fact that the IS-95 CDMA standard has to co-exist with AMPS standard signals in the same frequency band, this type of receiver has to tolerate an AMPS interferer that is approximately 74 dB higher than the CDMA signal at 900 KHz away from the center of the carrier. The receiver shown in FIG. 1 passes an incoming RF signal through an adjustable low noise amplifier (LNA) 103 into an RF saw filter 105. The input signal is than fed though a down conversion mixer 107 onto an IF SAW filter 109 providing approximately 30 dB of attenuation at 900 KHz. As typical with a ZIF receiver architecture, the signals then are split into I-Q components by mixing them using ZIF mixers 111,113 and local oscillator 115. This architecture relaxes the dynamic range requirements of the baseband filters 119,121 and the A/D converters 123,125 to the extent that 7-pole filters are used and there is only a need for a 6 bit A/D converter 123,125 in the I-Q signal chain.
The direct conversion receiver architecture shown in prior art FIG. 2 has demonstrated one viable solution in reducing cost and part count. In this architecture, no IF SAW filter is used. Thus, in order to provide the protection of IM distortion, 9-pole baseband filters 201,203 are used along with higher resolution A/D converters 205,207. The drawback of this architecture is a high current drain. In systems in which the received signal is slotted, such as GSM, the current can be reduced through duty cycles in a xe2x80x9cbattery savexe2x80x9d mode.
For example, if the current drain is approximately 100 milliamps (mA) during the active cycle and approximately zero mA for battery save cycles, the receiver is only in an xe2x80x9conxe2x80x9d mode only {fraction (1/10)}th of the talk time. Thus, the average total current drain is 10 mA i.e. (100 mA/10). This duty cycle technique cannot be used for most protocols and hence the current drain (100 mA) would be unacceptable. In further 3GPP systems, such as wide band CDMA (WCDMA), the receiver circuitry is kept active during the entire receive time. Existing land mobile radio analog frequency modulation (FM) systems operate continuously as well.
It is desirable to increase system linearity in the presence of strong on or off channel signals in order to avoid creating intermodulation (IM) products in the desired signal passband. Typically, system linearity can be improved by reducing gain before reaching the IM limiting stages. For some systems, it is desirable to use an amplifier with continuously variable gain to optimize the required gain reduction. At best, many of these continuously variable gain amplifiers have constant third order intercept (IM3) over their gain control range, and at the worst, the third order intercept degrades with increasing attenuation.
The gain controllable amplifiers are usually placed near the front of the radio frequency (RF) or intermediate frequency (IF) string in the receiver thus allowing for system intermediation improvements when gain is decreased. For large signals that require large amounts of gain reduction, the adjustable gain amplifier often becomes the limiting factor for receivers IM performance. In these circumstances, the designer of the stage would need to design an amplifier with sufficient current drain to give the IM performance required for strong signal conditions. This results in excess current drain for weak signal conditions when high linearity is not as important.
Hence, multi-mode receivers which can receive multiple types of MA""s will require A/D converters with a large dynamic range. Integrating active selectivity becomes increasingly difficult and consumes more current drain for multi-mode radios. With less active selectivity before the A/D, the dynamic range requirements increase. This, substantial increases in current are needed to maintain multi-mode receiver capabilities. One architecture that is being proposed for next generation CDMA and WCDMA standards is the direct conversion receiver. The IS-95 CDMA system standard is used to quantify the increase in the current drain of the direct conversion receiver compared to a dual conversion receiver.
Thus, the needs exists to provide a low noise amplifier and mixer system topology such that a decreased amount of dynamic range is required by the LNA plus mixer thereby requiring a lesser amount of current drain. This would have an overall effect of providing a more efficient amplifier plus mixer chain capable of handling a wide range of signal levels with relatively small current drain when integrated into a receiver integrated circuit (IC) package.